Reference is made to FIG. 1, which is a schematic diagram of a conventional test channel inside a chip tester. In general, a conventional chip tester has multiple test channels for transmitting test vectors. For each channel, the tester needs to generate two kinds of data. One is F data and the other is TG data. F data are primary data for testing the device under test (DUT) 11 and TG data are trigger signals for triggering the signal generating circuit 10.
Reference is made to FIG. 2, which is a schematic diagram of a conventional single digital word generator for producing TG data. As shown in the figure, the conventional single digital word generator has an edge-rising counter 102, an edge-falling counter 104 and a flip-flop component 12 (i.e. a latch component). The edge-rising counter 102 is used to preset the flip-flop component 12 to output a digital “1” (i.e. making the output of the flip-flop component 12 switch to high voltage) while the edge-falling counter 104 is used to clear the flip-flop component 12 to output a digital “0” (i.e. making the output of the flip-flop component 12 switch to low voltage).
However, if the tester needs to provide TG data for multiple test channels or provide TG data with multiple pulses for a single test channel, it needs to employ a plurality of single digital word generators correspondingly. Hence, large number of word generators will be required. Since both of the edge-rising counter 102 and edge-falling counter 104 are made of multiple flip-flop components, which have large volume and are costly, it will cause the conventional tester bulky and expensive.
Accordingly, as discussed above, the prior art still has some drawbacks that could be improved. The present invention aims to resolve the drawbacks in the prior art.